This invention relates generally to semiconductor integrated circuit manufacturing processes and more particularly, it relates to an improved method for forming a high voltage gate oxide for use with Flash EEPROM memory devices.
As is generally well-known in the semiconductor industry, there has been a continuing trend of integrating more and more different types of circuit devices onto a single semiconductor substrate. For example, the single semiconductor substrate may contain a floating gate memory device such as an Flash electrically, erasable programmable read-only (EEPROM) memory cell together with one or more high voltage devices and/or low voltage (logic) devices. A tunnel oxide formation used in the floating gate memory device requires typically a thin oxide layer of 100 xc3x85 or less in thickness. Due to its thinness and being subjected to high stress during operation, the tunnel oxide layer must be made robust so as to improve yield and reliability. Thus, the semiconductor industry has exposed the tunnel oxide layer to a nitrogen-containing environment in order to enhance its performance.
Unfortunately, in view of the high level of integration, while the nitrogen exposure process will improve the performance of the tunnel oxide layer in the floating gate memory device, it will substantially degrade the stability and performance of the peripheral (high voltage and low voltage) oxides subsequently formed for use in the high voltage devices and/or low voltage (logic) devices. This is due to the fact that nitrogen-containing surfaces are also created in the areas where the high and low voltage devices are to be subsequently formed as well as in the tunnel oxide layer of the single substrate. As a result, during the oxidation steps for forming the high voltage and low voltage oxides the remnant nitride in the nitrogen-containing surfaces will induce added defects or contamination in the peripheral oxides which adversely affects performance, such as reducing the breakdown voltage.
Therefore, there is still needed an improved method for forming peripheral oxides of a high quality and reliability for use with a Flash EEPROM memory device. It would be expedient that the method for forming the peripheral oxides be capable of being implemented with only minor modifications to the conventional EEPROM fabrication process. This is achieved in the present invention by forming either a sacrificial oxide layer or a high voltage oxide layer prior to the tunnel oxidation step so as to prevent degradation of the peripheral oxides subsequently formed.
Accordingly, it is a general object of the present invention to provide an improved method for forming a high voltage gate oxide which overcomes the problems encountered in the conventional EEPROM fabrication process.
It is an object of the present invention to provide an improved method for forming peripheral oxides of a high quality and reliability for use with a Flash EEPROM memory device.
It is another object of the present invention to provide a method for forming peripheral oxides of a high quality which can be implemented with only minor modifications to the conventional EEPROM fabrication process.
It is still another object of the present invention to provide a method for forming peripheral oxides of a high quality which includes an additional step of growing a sacrificial oxide layer prior to the step of performing a tunnel oxidation.
It is yet still another object of the present invention to provide a method for forming peripheral oxides of a high quality which includes an additional step of growing a high voltage gate oxide layer initially and etching off the same only above the tunnel oxide area prior to the step of performing a tunnel oxidation.
In accordance with a preferred embodiment of the present invention, there is provided a method for forming a high voltage gate oxide having a high quality and reliability for use with non-volatile memory devices. Field oxide isolation regions are formed in the top surface of a semiconductor substrate so as to define a first active region, a second active region, and a third active region. A sacrificial oxide layer is formed on the top surface of the semiconductor substrate and overlying the first active region, the second active region, and the third active region. The sacrificial oxide layer is removed from only the first active region. A tunnel oxide layer is then formed over the first active region and over the sacrificial oxide layer overlying the second active region and the third active region. A floating gate electrode, a dielectric layer over the floating gate electrode, and a control gate electrode over the dielectric layer are formed in the first active region so as to define a floating gate structure. The tunnel oxide layer and the sacrificial oxide layer over the respective second active region and the third active region are removed subsequent to the forming of the floating gate structure. A high voltage gate oxide layer is formed over the second active region and the third active region. The high voltage oxide layer is then removed from only the third active region. A low voltage gate oxide layer is formed over the third active region.